Software-based Electronic Design Automation (EDA) tools, in general, can process circuit designs through what is referred to as an implementation flow. Processing the circuit design through an implementation flow prepares the circuit design for implementation within a particular integrated circuit (IC). A typical implementation flow entails various processes such as synthesis, technology mapping, placing, and routing. In the case of a programmable logic device (PLD) such as a field programmable gate array (FPGA), the resulting circuit design can be transformed into a bitstream that, when loaded into an IC (the target device), configures the target device to implement the circuit design.
Synthesis generally refers to the process of converting a hardware description language (HDL) description of a circuit design into a low-level implementation of the circuit design using logic gates. A programmatic circuit design written in an HDL can be compiled into a gate level description. Technology mapping generally refers to the process of associating the logic gates of the synthesized circuit design with physical circuit components available on the target device, e.g., memory, look-up tables, etc. The resulting circuit design can be specified in terms of components available on the target device rather than in terms of more primitive logic gates.
Placement generally refers to the process of assigning the technology mapped circuit components to actual locations on the target device. Routing generally refers to the process of linking the placed circuit components with wires or appropriate interconnect circuitry to facilitate communication and signal exchange among the components. These steps may be performed whether the circuit design is to be implemented within an application specific integrated circuit (ASIC) or a PLD.
Some implementation flows apply each process in serial. The decisions made within an earlier process, such as synthesis, will influence the decisions and results obtained during later processes, e.g., placement and/or routing. Processes that occur earlier within an implementation flow try to predict the decisions that will be made during later processes in an attempt to make the correct or optimal implementation decision(s). Each process typically makes decisions according to various costs relating to a design objective, e.g., timing, area usage, power consumption, or the like. The metrics used, however, have proven to be ineffective in determining the overall quality of the resulting circuit implementation. In other words, metrics that indicate the “goodness” of a logical network are often not particularly good indicators of the quality or goodness of the resulting physical circuit implementation.
Other implementation flows incorporate feedback mechanisms. Feedback mechanisms, however, still rely upon metrics applied to the logical network that may or may not serve as reliable indicators of a quality physical circuit implementation. Accordingly, despite the improvements obtained through the use of feedback mechanisms, many circuit designers still find randomization tools useful. A randomization tool processes the circuit design through multiple implementation flows. During each implementation flow, the randomization tool varies some aspect or implementation parameter(s) of one or more processes of the implementation flow in an attempt to explore alternate implementations of the circuit design. Often, the randomization tool is able to improve upon the circuit implementation, which demonstrates the often loose correlation that exists between measures of goodness of a logical network and goodness of the resulting physical circuit implementation. However, randomization tools typically require significant time to complete execution, which limits their usefulness. For example, a randomization tool often may operate overnight or over several days to explore different implementations of a circuit design.
The present invention may address one or more of these issues.